FECs
The IP Core implements CCSDS 231.0 LDPC.
Key Features:
- Compliant with CCSDS 231.0-B-4 Standard, July 2021, TC synchronization and channel coding
- Supports both (128, 64) and (512, 256) LDPC encoding schemes
- Encoding rate up to 200 Mbit/s
- Decoding rate up to 120 Mbit/s
- On-the-fly block type change
- Layered Min-Sum-Offset decoding with low implementation loss
- Decoding early termination mechanism
- Variable number of decoding iterations up to 256
Version : 1.0
Build date : 2022.08
Ordering code : ip-ccsds-231-ldpc-encoder-decoder
Supported technologies : FPGA (Xilinx, Intel/Altera, Lattice, Microsemi/Actel)
The IP Core resource utilization and performance : Specification (PDF)
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