FECs
The IP Core implements the LDPC error-correcting coding to specification CCSDS (8160, 7136) redundant 223/255, supporting both continuous and burst modes. It is fully compatible with the CCSDS 131.0-B-4 TM Synchronization and Channel Coding standard.
Version : 2.0
Build date : 2014.09
Ordering code : ip-ldpc-nasa-codec
Supported technologies : FPGA (Xilinx, Intel/Altera, Lattice, Microsemi/Actel), ASIC (Digital ASIC)
The IP Core resource utilization and performance : Specification (PDF)
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