FECs
The IP Core implements BCH Code encoding and decoding.
Key Features:
- Fully customizable to any standard, including NAND Flash and DVB
- Pipelined parallel Encoder and Decoder design
- High error correction performance
- Decoding status reporting
- Throughput up to 500 MBytes/s
- Code block length (N) up to 8191 bytes
- Payload length (K) up to 8190 bytes
- Parity length up to 1536 bits
Version : 1.0
Build date : 2024.11
Ordering code : ip-bch-encoder-decoder
Supported technologies : FPGA (Xilinx, Intel/Altera, Lattice, Microsemi/Actel)
The IP Core resource utilization and performance : Specification (PDF)
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